Job Role: Intern (Technical-Engineering) – Hardware Verification Engineer (Intern)

Eligibility: B.E./B.Tech, M.E./M.Tech

Job Location: Hyderabad

Experience Required: Freshers

Last Date To Apply: As Soon As Possible

Candidate Profile and Criteria:

  • This hiring of Synopsys is for candidates who have Bachelor’s degree in engineering as a minimum.
  • Requires a 0+ years of related experience.
  • Candidate should have good digital design knowledge.
  • Microprocessor architecture knowledge is a big plus.
  • Candidate should have good written, verbal and analytical skills desired.
  • Experience in following areas is preferred :
    HDL and Verification languages: SystemVerilog, Verilog.
  • Programming skills  : C, C++, assembly, Perl, makefile generation.
  • Tools: RTL Simulators, eg VCS.

Company Profile:

Company’s Name: Synopsys

Company’s Website: www.synopsys.com

Synopsys is founded in 1986 by Dr. Aart de Geus and a team of engineers from General Electric’s Microelectronics Center in Research Triangle Park, North Carolina, Synopsys was first established as “Optimal Solutions” with a charter to develop and market ground-breaking synthesis technology developed by the team at General Electric. The company pioneered the commercial application of logic synthesis that has since been adopted by every major semiconductor design company in the world. This technology provided an exponential leap in integrated circuit (IC) design productivity by allowing engineers to specify chip functionality at a higher level of abstraction. Without this technology, the complex designs of today would not be possible. Today, as a leader in electronic design automation (EDA) and semiconductor intellectual property (IP), Synopsys continues to deliver products and services that accelerate innovation in the global electronics market.

Job Details and Description:

  • The candidate will be a key member of the Synopsys Design Ware ARC Processor hardware team.
  • Responsibility includes development of Verification Testbenches and automation, creation of tests – both directed and random, functional coverage model creation and report analysis, code coverage analysis, development of C-models, resolving mismatches between design and C-model, integration of third party and internal verification IP, regression management, review and improvement of verification test suites.




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