Maxim Integrated Hiring Fresher/ Experience Across India

Jobs In Gandhinagar| Maxim Integrated| Recruitment| 2017 Batch| 2018 batch| 2019 Batch| 2020 Batch| B.E./B.Tech| M.E./M.Tech| MSc| Freshers Jobs| 0-3 Years| Experience Jobs

Maxim Integrated hiring freshers/ experience (0-3 Years) as Yield Engineer in Gandhinagar. Candidates from 2017 Batch, 2018 batch, 2019 Batch or 2020 Batch with B.E./B.Tech, M.E./M.Tech, MSc degree are eligible for this job opening. Details related to this Maxim Integrated job opening are given below.

Maxim Integrated Job Opening Summary

Job Role: Yield Engineer

Eligibility: B.E./B.Tech, M.E./M.Tech, MSc

Job Location: Bangalore

Experience Required: Fresher/ Experience (0-3 Years)

Last Date To Apply: As Soon As Possible

Salary: Not Disclosed

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Candidate Profile and Criteria

• This recruitment of Maxim Integrated is for candidates who have completed B.E./B.Tech/ M.E./M.Tech (Electronics/ Electrical/ Instrumentation), MSc (Physics or Electronics) from a reputed institute.
• Candidate should have minimum of 70%/~7+ CGPA aggregate score.
• Preferred work experience in any industrial domain for around 0-3 years.
• Work experience in allied domains like LED, Solar and CMOS research/projects will be given preference.
• Excellent knowledge of basic science concepts in physics, chemistry, and electronics
• Good knowledge of CMOS device physics (desirable) and basic electronics
• Excellent written and verbal English communication skills
• Good knowledge of MS office tools (word, excel, and PowerPoint)
• Knowledge of semiconductor wafer fabrication process (desirable)
• Should possess good interpersonal skills
• Problem-solving and analytical skills
• Result-orientation and attention to details
• Experience in semiconductor manufacturing/testing, yield engineering, or statistical processes domain is an added advantage
• Candidates from Gandhinagar / Ahmedabad preferable.
• He/She should be willing to work in flexible timings (including night shifts) and flexible weekday (including Saturday and Sunday) schedule which will depend upon project schedules and deadlines.
• Good team player and can smoothly work with cross-functional team across the globe

Company Profile

Company’s Name: Maxim Integrated
Company’s Website: www.maximintegrated.com
Every day, electronic devices are becoming smarter with greater integration. Body sensors can monitor our health. Cars can drive themselves. Networked homes can power up when needed. At Maxim Integrated, we’re solving engineering problems and empowering design innovation, enabling our customers to create products that shape our world. Our innovative and high-performance analog and mixed-signal products and technologies make systems smaller and smarter, with enhanced security and increased energy efficiency.

Roles and Responsibilities

• Review and compile classification of defects identified during semiconductor manufacturing processes.
• Define and maintain relevant defect matrixes for product performance, reliability, and yield.
• Analyze semiconductor wafer data for patterns and signatures.
• Design and maintain SPC charts for excursion detection and control.
• Look out for possible excursions during wafer processing.
• Real-Time Analysis of Inline fab data on defects, tool status, commonality, and RCA.
• Required to be hands-on in the day-to-day review of information, evaluation of defect monitoring strategies, and understanding of defect mechanisms with the mindset of making a difference. 
• Perform root cause analysis for low yields using various advanced data analysis tools
• Statistical and root cause analysis of sort test and parametric test data.
• Should be willing to work with flexible timings which can over-lap US/global time zones.
• Regular excellent interaction with remote US/global teams for projects and resolving yield issues.
• Own product/product line/technology to improve product/technology health and disposition of hold material with the highest accuracy and within target cycle time.
• Identify systematic issues and D0/Cpk opportunity and drive them to fix
• Connect failure at PT or wafer sort to inline/defect modes with driving fix
• Identify test issues and work closely with test floor/PT to fix

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How To Apply